The cost of the semiconductor material used to fabricate an integrated circuit device having a high capacity of logic gates is a function of the yield (Y) of a particular fabrication process. The yield is a function of the area (A) of the die which forms the basis for the device and the defect density (DD) of the fabrication process. If the defects generated during the fabrication process are assumed to be random and as having a Poisson distribution, the following formula for the yield is obtained: EQU Y=e.sup.-( DD*A) (1)
Based on these assumptions, the cost of manufacturing the semiconductor material increases exponentially with an increase in the die area.
Given that the die area required to implement a single gate is fixed, gate capacity will vary linearly with die area. Therefore, based on the yield formula given above, the cost of manufacturing the semiconductor materials increases at a rate greater than that at which the number of logic gates increases.
The non-linear increase of the semiconductor cost as a function of the gate capacity means that the cost of fabricating complex devices can quickly become prohibitively expensive for many applications. This creates a strong disincentive to using high gate capacity devices, even for applications which might benefit from such use.
For example, if a device having 60K (thousand) programmable logic gates is to be made on a single die using a 0.8 micron CMOS process, a square die approximately 2.5 cm on a side would be required. This die has a surface area of 6.25 cm.sup.2, and based on the yield formula given in equation (1) and an assumed defect density of 1 per cm.sup.2, the yield would be about 0.002 or 0.2%. Assuming 16 gross die per six inch diameter wafer and that such a wafer of silicon costs approximately $1,000 when fully processed, this yield gives a cost per die of approximately $31,250. If a defect density of 0.5 per cm.sup.2 is used, the yield obtained from equation (1) increases to 4.4%. This yield gives a cost per die of approximately $1,420. However, even with the increased yield which results from the lower defect density, the cost of the processed silicon required to fabricate the 60 k device may still be too much for some applications which would benefit from the increased gate capacity.
The high cost of the silicon used in making a single high capacity chip has provided the motivation for developing alternative ways of fabricating high gate capacity devices. One of these alternatives is based on Multi-Chip Module (MCM) packaging technology. MCM technology combines two or more individual chips into a single package which is capable of performing more complex functions than a single chip. The individual chips are mounted on a common substrate and connected to each other and to the package contacts by one of several methods, for example, wire bonding or solder bump technology. In the case of programmable logic devices, the number of interconnections between the chips has a significant impact on the degree of utilization (the ratio of gates used to gates available) that can be achieved for a given application. This is important because it determines how effectively the chips function as a single unit and the complexity of the functions which the combination of chips can perform.
Wire bonding is commonly used in MCM packages to connect the chips to a common substrate because the chips which are usually combined into a MCM package are of the type which are meant to be used individually, and hence are designed to be mounted using wire bonding. However, wire bonding has several disadvantages when used in MCM packages:
(1) the density of the interconnections between a chip and the substrate and between individual chips is constrained by the physical space available for the wires, thereby limiting the number of interconnections possible; (2) the number of interconnections must be limited in order to prevent short circuits; and (3) capacitive and inductive coupling between the leads can impact performance.
Another method for mounting individual chips to a common substrate is to use solder bump, or flip-chip technology. In this method, solder bumps are placed on the die and the chip is flipped over, placing the solder bumps in contact with conductive pads on the substrate. The solder is then reflowed, establishing a good electrical contact. The individual chips are interconnected using an interconnect network on or within the substrate.
An example of a MCM technology which is suited for applications requiring a high interconnect density between the individual chips and which uses such an interconnect network is Area Array technology. In this packaging method, connections are made from the interior of one chip to another through a multi-layer MCM substrate. The interconnect layers of the substrate are accessed through arrays of conductive pads which are designed to correspond to the positions of the metal bumps on chips used in flip-chip packaging methods. The metal bumps are soldered to the array pads to electrically connect the chips to each other.
While the flip-chip mounting method minimizes the chip-to-chip spacing and significantly reduces the likelihood of a short circuit and the magnitude of capacitive and inductive coupling, it does not resolve a problem common to both wire bonding and flip-chip mounting technologies. This problem relates to how to combine individual chips into a programmable logic device that has a utilizable gate capacity equal to the sum of the gate capacities of the individual chips.
Currently, MCM programmable devices require special development tools which partition the logical functions which are to be implemented by the complete package into those performed by each of the individual chips, taking into account the limited interconnect capacity between the chips. This type of tool is required in addition to the regular development tools used to design an individual chip. However, even with such special design tools, overall logic gate utilization in the MCM package is lower than could be obtained for a single chip having the same gate capacity. This is due to the limited number of interconnections possible and the resultant I/O bottlenecks between the individual chips.
What is desired is an architecture for a large gate capacity programmable device in which the cost of the semiconductor material increases linearly with gate capacity, and which maintains a constant gate utilization percentage as the total gate capacity increases.